Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since such devices were first introduced several decades ago. Integrated circuits (ICs) have generally followed “Moore's Law,” meaning that the number of devices which will fit on a single integrated circuit chip doubles every two years. Today's IC fabrication facilities routinely produce 65 nm (0.065 μm) feature size devices, and future fabs will soon be producing devices having even smaller feature sizes.
Not surprisingly, semiconductor integrated circuit fabrication is a complicated process involving a coordinated series of accurate, precise, and repeatable operations. During the fabrication operations, surfaces of a semiconductor substrate (e.g., a semiconductor wafer) become contaminated with layers of residue comprised of particulates, organic materials, metallic impurities (e.g., copper (Cu), aluminum (Al), titanium (Ti), and tungsten (W)), and native oxides (e.g., silicon dioxide).
An increasingly important task in semiconductor processing is the cleaning and preparation of the wafer surface prior to subsequent processing steps. A goal of this cleaning is to remove contaminants and native oxides from wafer surfaces. Wafer cleaning is, in fact, the most frequently repeated operation in integrated circuit fabrication and is one of the most important segments in the semiconductor-equipment business. However, each integrated circuit device generation becomes increasingly difficult to properly clean.
For example, roughly 20% of all process steps in a contemporary fab are cleaning steps. The percentage of cleaning steps continues to increase with each advance in design rules. While the number of cleanings increases, the requirement levels for impurity concentrations, particle size and quantity, water and chemical usage, and the amount of surface microroughness continues to increase as well. Not only is wafer cleaning needed now before each new process sequence, but also additional steps are often required to clean fab process tools after a production run.
Two major types of cleaning processes exist: wet cleaning methods and dry cleaning methods. Liquid chemical cleaning processes, generally referred to as wet cleaning, rely on a combination of solvents, acids, and water to spray, scrub, etch, and dissolve contaminants from the wafer surface. Dry cleaning processes use gas phase chemistry, and rely on chemical reactions required for wafer cleaning, as well as other techniques such as lases, ions, aerosols, and ozonated chemistries. Generally, dry cleaning methods use fewer chemicals and are less hazardous for the environment but usually do not perform as well as wet methods, especially for particle removal.
For wet-chemical cleaning methods, the RCA clean, developed in 1965, still forms the basis for most front-end-of-line (FEOL) wet cleans. A typical RCA-type cleaning sequence starts with the use of a sulfuric acid/hydrogen peroxide (H2SO4/H2O2, commonly called a “piranha etch”) solution followed by a dip in diluted hydrofluoric acid (HF). A standard clean first operation (“SC-1 clean”) uses a solution of ammonium hydroxide/hydrogen peroxide/water (NH4OH/H2O2/H2O, also known as a “base piranha”) to remove particles, while a standard clean second operation (“SC-2 clean”) uses a solution of hydrochloric acid/hydrogen peroxide/water (HCl/H2O2/H2O) to remove metals. Despite increasingly stringent process demands and enhanced improvements in analytical techniques, cleanliness of chemicals, and deionized (DI) water, the basic cleaning recipes have remained generally unchanged since the first introduction of this cleaning technology. Since environmental concerns and cost-effectiveness were not a major issue 40 years ago, the RCA cleaning procedure is far from optimal in these respects and must therefore be applied efficiently and cost-effectively.
Perhaps more importantly, from a yield and cost basis standpoint, the type of equipment used in the clean process is becoming a primary driver. The clean process must be effective, but it must also be fast. Contemporary throughput demands for current generation 300 mm wafers are 360 wafers per hour. Presently, systems use a linear wafer motion requiring a non-productive time period while the wafer carrier is returned to the starting point in a wafer cleaning tool. Thus, wafer handling is slow. Proposed solutions to increase throughput have focused on joining a plurality of cleaning tools in parallel. While such solutions increase substrate throughput, they do so at the expense of tool footprint, increased equipment cost, and reduced reliability.
Currently available semiconductor substrate cleaning equipment suffers from a high cost-per-unit of wafer cleaned, a high cost-of-ownership, a lack of scalability, and an inability to easily adapt to various processing sequences or to increases in semiconductor wafer sizes. Among the many factors that contribute to wafer cleaning costs, the capital cost of wafer handlers which move semiconductor wafers between various locations presents a significant expense. Accordingly, improvements are needed in the field of semiconductor wafer cleaning with a special emphasis on equipment reliability, throughput, and efficiency.